forked from github/verilator
19 lines
366 B
Systemverilog
19 lines
366 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module pre_no_ts;
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endmodule
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`timescale 1ns/1ns
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module t;
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pre_no_ts pre_no_ts();
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post_no_ts pst_no_ts();
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endmodule
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module post_no_ts;
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endmodule
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