forked from github/verilator
28 lines
430 B
Systemverilog
28 lines
430 B
Systemverilog
module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int pos;
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int a;
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int b;
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int array[2][2] = '{ '{0, 1}, '{2, 3}};
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string test_string = "abcd";
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initial begin
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if (0 && test_string[pos++] != "e");
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if (1 || pos-- != 1);
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if (a <-> --b);
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if (0 -> ++b);
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pos = (a > 0) ? a++ : --b;
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pos = array[0][0]++;
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end
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assert property (@(posedge clk) a++ >= 0);
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endmodule
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