forked from github/verilator
2ce30e78a1
git-svn-id: file://localhost/svn/verilator/trunk/verilator@843 77ca24e4-aefa-0310-84f0-b9a241c72d87
38 lines
788 B
Verilog
38 lines
788 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_inst_a (/*AUTOARG*/
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// Outputs
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o_w5, o_w5_d1r, o_w40, o_w104,
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// Inputs
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clk, i_w5, i_w40, i_w104
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);
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input clk;
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input [4:0] i_w5;
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output [4:0] o_w5;
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output [4:0] o_w5_d1r;
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input [39:0] i_w40;
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output [39:0] o_w40;
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input [104:0] i_w104;
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output [104:0] o_w104;
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wire [4:0] o_w5 = i_w5;
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wire [39:0] o_w40 = i_w40;
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wire [104:0] o_w104 = i_w104;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [4:0] o_w5_d1r;
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// End of automatics
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always @ (posedge clk) begin
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o_w5_d1r <= i_w5;
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end
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endmodule
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