forked from github/verilator
56 lines
1.3 KiB
Systemverilog
56 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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int fd;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 5) begin
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fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w");
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end
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else if (cyc == 10) begin
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$fstrobe(fd, "[%0t] cyc=%0d", $time, cyc);
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$fstrobe(fd, "[%0t] cyc=%0d also", $time, cyc);
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end
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else if (cyc == 17) begin
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$fstrobeb(fd, cyc, "b");
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end
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else if (cyc == 18) begin
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$fstrobeh(fd, cyc, "h");
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end
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else if (cyc == 19) begin
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$fstrobeo(fd, cyc, "o");
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end
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else if (cyc == 22) begin
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$fstrobe(fd, "[%0t] cyc=%0d new-strobe", $time, cyc);
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end
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else if (cyc == 24) begin
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$monitoroff;
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end
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else if (cyc == 26) begin
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$monitoron;
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end
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else if (cyc == 27) begin
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$fclose(fd);
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end
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else if (cyc == 30) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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