forked from github/verilator
13 lines
803 B
Plaintext
13 lines
803 B
Plaintext
%Warning-LATCH: t/t_lint_latch_bad_3.v:18:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value)
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: ... Suggest use of always_latch for intentional latches
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18 | always @(reset or en or a or b)
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| ^~~~~~
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... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.
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%Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Delayed assignments (<=) in non-clocked (non flop or latch) block
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: ... Suggest blocking assignments (=)
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70 | o4 <= 1'b0;
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| ^~
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*** See the manual before disabling this,
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else you may end up with different sim results.
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%Error: Exiting due to
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