forked from github/verilator
52912c6329
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29 lines
626 B
Verilog
29 lines
626 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`include "verilated.v"
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module t_clk_two (/*AUTOARG*/
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// Inputs
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fastclk, reset_l
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);
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input fastclk;
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input reset_l;
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// verilator lint_off GENCLK
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reg clk2;
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// verilator lint_on GENCLK
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reg [31:0] count;
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wire reset_h = ~reset_l;
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always @ (posedge fastclk) begin
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if (reset_h) clk2 <= 0;
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else clk2 <= ~clk2;
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end
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always @ (posedge clk2) begin
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if (reset_h) count <= 0;
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else count <= count + 1;
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end
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endmodule
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