forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
32 lines
489 B
Verilog
32 lines
489 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module a;
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c c ();
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initial begin
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$write("Bad top modules\n");
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$stop;
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end
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endmodule
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module b;
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d d ();
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endmodule
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module c;
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initial begin
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$write("Bad top modules\n");
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$stop;
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end
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endmodule
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module d;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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