forked from github/verilator
12 lines
566 B
Plaintext
12 lines
566 B
Plaintext
%Error: t/t_var_bad_sv.v:8:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
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... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
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8 | reg do;
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| ^~
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%Error: t/t_var_bad_sv.v:9:14: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
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9 | mod mod (.do(bar));
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| ^~
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%Error: t/t_var_bad_sv.v:9:16: syntax error, unexpected '(', expecting ')'
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9 | mod mod (.do(bar));
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| ^
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%Error: Exiting due to
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