forked from github/verilator
5d98035170
cint.mainInt(nodep) walks the tree and populates m_ctorVarsVec. Reuse EmitCImp cint for the slow mainImp() emition steps to make sure we emit constructor calls to setup SystemC sc_module names.
31 lines
781 B
Perl
Executable File
31 lines
781 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2020 by Edgar E. Iglesias. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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if (!$Self->have_sc) {
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skip("No SystemC installed");
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}
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else {
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top_filename("t/t_sc_names.v");
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compile(
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make_main => 0,
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verilator_flags2 => ["-sc --exe $Self->{t_dir}/t_sc_names.cpp"],
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);
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execute(
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check_finished => 1,
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);
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}
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ok(1);
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1;
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