forked from github/verilator
67 lines
1.7 KiB
Systemverilog
67 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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typedef string sarray_t[2];
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typedef sarray_t q_sarray_t[$];
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typedef bit [95:0] wide_t;
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typedef wide_t warray_t[2];
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typedef warray_t q_warray_t[$];
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initial begin
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begin
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q_sarray_t iq;
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sarray_t a;
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sarray_t b0;
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sarray_t b1;
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a[0] = "hello";
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a[1] = "world";
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iq.push_back(a);
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a[0] = "bye";
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a[1] = "world";
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iq.push_back(a);
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b0 = iq[0];
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b1 = iq[1];
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`checks(b0[0], "hello");
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`checks(b0[1], "world");
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`checks(b1[0], "bye");
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`checks(b1[1], "world");
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end
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`ifndef verilator
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// Need wide conversion into VlUnpacked types
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// If we convert all arrays to VlUnpacked it works, so we need to track
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// data types and insert conversions perhaps in V3Cast, but we currently
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// don't know the output datatypes, so work needed.
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begin
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q_warray_t iq;
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warray_t a;
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warray_t b0;
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a[0] = "abcdefg_ijkl";
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a[1] = "012123123128";
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iq.push_back(a);
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b0 = iq[0];
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`checks(b0[0], "abcdefg_ijkl");
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`checks(b0[1], "012123123128");
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end
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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