forked from github/verilator
19 lines
296 B
Systemverilog
19 lines
296 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//See bug289
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`elsif A
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`endif
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`else
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`endif
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`error `include
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module t;
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endmodule
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