forked from github/verilator
12 lines
310 B
Systemverilog
12 lines
310 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`include "t_pp_lib_inc.vh"
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module t();
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wire [`WIDTH-1:0] a;
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library_cell n1(a);
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endmodule
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