forked from github/verilator
18 lines
421 B
Systemverilog
18 lines
421 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off UNDRIVEN
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module t();
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wire sig;
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sub sub0(.out(33'b0));
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sub sub1(.out({32'b0, sig}));
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sub sub2(.out({32'b1, sig}));
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endmodule
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module sub(output reg [32 : 0] out);
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endmodule
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