forked from github/verilator
1c1b95161b
* Add a test to make sure that lib modules (loaded via -y option) can be a hier_block. * Add HDL file of the hier_block to the source list if the module is loaded via -y option. (Each hier_block is treated as a top module when processing the hier_block.) * Use "\n" for delimiter as the other files
24 lines
695 B
Perl
Executable File
24 lines
695 B
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(vlt_all => 1);
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compile(
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verilator_flags2 => ['--hierarchical',
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'-y', $Self->{t_dir} . '/t_flag_relinc_dir/chip',
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'+incdir+'. $Self->{t_dir} . '/t_flag_relinc_dir/include'],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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