forked from github/verilator
52 lines
1.0 KiB
Systemverilog
52 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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static task static_task(int x);
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$write("Called static task: %d\n", x);
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if (x != 16) $stop;
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endtask
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static function int static_function(int x);
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$write("Called static function: %d\n", x);
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if (x != 23) $stop;
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return 42;
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endfunction
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endclass : Cls
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class OCls;
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int i;
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static function OCls create();
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OCls o = new;
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o.i = 42;
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return o;
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endfunction
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static task test_obj(OCls o);
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if (o.i != 42) $stop;
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endtask
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endclass
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module t (/*AUTOARG*/);
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initial begin
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int x;
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OCls oc;
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Cls::static_task(16);
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x = Cls::static_function(23);
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$write("Static function result: %d\n", x);
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if (x != 42) $stop;
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oc = OCls::create();
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OCls::test_obj(oc);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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