forked from github/verilator
1058 lines
52 KiB
C++
1058 lines
52 KiB
C++
/* -*- C++ -*- */
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/**************************************************************************
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* DESCRIPTION: Verilator: Flex input file
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*
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* Code available from: https://verilator.org
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*
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**************************************************************************
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*
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* Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you
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* can redistribute it and/or modify it under the terms of either the
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* GNU Lesser General Public License Version 3 or the Perl Artistic License
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* Version 2.0.
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* SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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*
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*************************************************************************/
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/* clang-format off */
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%option interactive c++ stack noyywrap
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%{
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/* %option nodefault */
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#ifdef NEVER_JUST_FOR_CLANG_FORMAT
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}
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#endif
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// clang-format on
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#include "V3Number.h"
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#include "V3ParseImp.h" // Defines YYTYPE; before including bison header
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#include "V3ParseBison.h" // Generated by bison
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extern void yyerror(const char*);
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extern void yyerrorf(const char* format, ...);
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#define STATE_VERILOG_RECENT S17 // State name for most recent Verilog Version
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#define PARSEP V3ParseImp::parsep()
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#define SYMP PARSEP->symp()
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#define YY_INPUT(buf, result, max_size) \
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do { result = PARSEP->flexPpInputToLex(buf, max_size); } while (false)
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//======================================================================
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#define FL_FWD (PARSEP->fileline()->forwardToken(yytext, yyleng, true))
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// Use this to break between tokens whereever not return'ing a token (e.g. skipping inside lexer)
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#define FL_BRK (PARSEP->fileline()->startToken())
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#define CRELINE() (PARSEP->copyOrSameFileLine())
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#define FL \
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do { \
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FL_FWD; \
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yylval.fl = CRELINE(); \
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} while (false)
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#define ERROR_RSVD_WORD(language) \
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do { \
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FL_FWD; \
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yyerrorf("Unsupported: " language " reserved word not implemented: '%s'", yytext); \
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FL_BRK; \
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} while (0)
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//======================================================================
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void yyerror(const char* errmsg) {
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PARSEP->fileline()->v3error(errmsg);
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static const char* const colonmsg = "syntax error, unexpected ::, ";
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// tokens;
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if (0 == strncmp(errmsg, colonmsg, strlen(colonmsg))
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&& PARSEP->prevBisonVal().token == yaID__ETC
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&& PARSEP->curBisonVal().token == yP_COLONCOLON) {
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static int warned = false;
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if (!warned++) {
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std::cerr << PARSEP->fileline()->warnMore()
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<< ("... Perhaps '" + *PARSEP->prevBisonVal().strp
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+ "' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)")
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<< std::endl;
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}
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}
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}
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void yyerrorf(const char* format, ...) {
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const int maxlen = 2000;
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char msg[maxlen];
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va_list ap;
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va_start(ap, format);
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VL_VSNPRINTF(msg, maxlen, format, ap);
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msg[maxlen - 1] = '\0';
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va_end(ap);
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yyerror(msg);
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}
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// clang-format off
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/**********************************************************************/
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%}
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%e 2000
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%p 5000
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%n 2500
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%k 1000
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%a 15000
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%o 25000
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%s V95 V01 V05 S05 S09 S12 S17
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%s STRING ATTRMODE TABLE
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%s VA5 SAX VLT
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%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
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%s IGNORE
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ws [ \t\f\r]+
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wsnr [ \t\f]+
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crnl [\r]*[\n]
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/* identifier */
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id [a-zA-Z_][a-zA-Z0-9_$]*
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/* escaped identifier */
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escid \\[^ \t\f\r\n]+
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word [a-zA-Z0-9_]+
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/* verilog numbers, constructed to not match the ' that begins a '( or '{ */
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vnum1 [0-9]*?[''][sS]?[bcodhBCODH][ \t\n]*[A-Fa-f0-9xXzZ_?]*
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vnum2 [0-9]*?[''][sS]?[01xXzZ]
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vnum3 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH]?[ \t\n]*[A-Fa-f0-9xXzZ_?]+
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vnum4 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH]
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vnum5 [0-9][_0-9]*[ \t\n]*[''][sS]
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vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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%%
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<INITIAL>.|\n {BEGIN STATE_VERILOG_RECENT; yyless(0); }
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/************************************************************************/
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/* Verilator control files */
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<VLT>{
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{ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */
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{crnl} { FL_FWD; FL_BRK; } /* Count line numbers */
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"clock_enable" { FL; return yVLT_CLOCK_ENABLE; }
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"clocker" { FL; return yVLT_CLOCKER; }
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"coverage_block_off" { FL; return yVLT_COVERAGE_BLOCK_OFF; }
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"coverage_off" { FL; return yVLT_COVERAGE_OFF; }
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"coverage_on" { FL; return yVLT_COVERAGE_ON; }
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"full_case" { FL; return yVLT_FULL_CASE; }
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"inline" { FL; return yVLT_INLINE; }
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"isolate_assignments" { FL; return yVLT_ISOLATE_ASSIGNMENTS; }
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"lint_off" { FL; return yVLT_LINT_OFF; }
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"lint_on" { FL; return yVLT_LINT_ON; }
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"no_clocker" { FL; return yVLT_NO_CLOCKER; }
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"no_inline" { FL; return yVLT_NO_INLINE; }
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"parallel_case" { FL; return yVLT_PARALLEL_CASE; }
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"public" { FL; return yVLT_PUBLIC; }
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"public_flat" { FL; return yVLT_PUBLIC_FLAT; }
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"public_flat_rd" { FL; return yVLT_PUBLIC_FLAT_RD; }
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"public_flat_rw" { FL; return yVLT_PUBLIC_FLAT_RW; }
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"public_module" { FL; return yVLT_PUBLIC_MODULE; }
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"sc_bv" { FL; return yVLT_SC_BV; }
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"sformat" { FL; return yVLT_SFORMAT; }
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"split_var" { FL; return yVLT_SPLIT_VAR; }
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"tracing_off" { FL; return yVLT_TRACING_OFF; }
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"tracing_on" { FL; return yVLT_TRACING_ON; }
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-?"-block" { FL; return yVLT_D_BLOCK; }
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-?"-file" { FL; return yVLT_D_FILE; }
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-?"-function" { FL; return yVLT_D_FUNCTION; }
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-?"-lines" { FL; return yVLT_D_LINES; }
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-?"-match" { FL; return yVLT_D_MATCH; }
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-?"-module" { FL; return yVLT_D_MODULE; }
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-?"-msg" { FL; return yVLT_D_MSG; }
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-?"-rule" { FL; return yVLT_D_RULE; }
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-?"-task" { FL; return yVLT_D_TASK; }
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-?"-var" { FL; return yVLT_D_VAR; }
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/* Reachable by attr_event_control */
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"edge" { FL; return yEDGE; }
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"negedge" { FL; return yNEGEDGE; }
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"or" { FL; return yOR; }
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"posedge" { FL; return yPOSEDGE; }
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}
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/************************************************************************/
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/* Verilog 1995 */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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{ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */
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{crnl} { FL_FWD; FL_BRK; } /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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"$c"[0-9]* { FL; return yD_C; } /*Verilator only*/
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/* System Tasks */
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"$acos" { FL; return yD_ACOS; }
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"$acosh" { FL; return yD_ACOSH; }
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"$asin" { FL; return yD_ASIN; }
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"$asinh" { FL; return yD_ASINH; }
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"$atan" { FL; return yD_ATAN; }
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"$atan2" { FL; return yD_ATAN2; }
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"$atanh" { FL; return yD_ATANH; }
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"$bitstoreal" { FL; return yD_BITSTOREAL; }
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"$bitstoshortreal" { FL; return yD_BITSTOSHORTREAL; }
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"$ceil" { FL; return yD_CEIL; }
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"$cos" { FL; return yD_COS; }
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"$cosh" { FL; return yD_COSH; }
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"$display" { FL; return yD_DISPLAY; }
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"$displayb" { FL; return yD_DISPLAYB; }
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"$displayh" { FL; return yD_DISPLAYH; }
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"$displayo" { FL; return yD_DISPLAYO; }
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"$dumpall" { FL; return yD_DUMPALL; }
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"$dumpfile" { FL; return yD_DUMPFILE; }
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"$dumpflush" { FL; return yD_DUMPFLUSH; }
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"$dumplimit" { FL; return yD_DUMPLIMIT; }
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"$dumpoff" { FL; return yD_DUMPOFF; }
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"$dumpon" { FL; return yD_DUMPON; }
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"$dumpports" { FL; return yD_DUMPPORTS; }
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"$dumpportsall" { FL; return yD_DUMPALL; }
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"$dumpportsflush" { FL; return yD_DUMPFLUSH; }
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"$dumpportslimit" { FL; return yD_DUMPLIMIT; }
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"$dumpportsoff" { FL; return yD_DUMPOFF; }
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"$dumpportson" { FL; return yD_DUMPON; }
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"$dumpvars" { FL; return yD_DUMPVARS; }
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"$exp" { FL; return yD_EXP; }
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"$fclose" { FL; return yD_FCLOSE; }
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"$fdisplay" { FL; return yD_FDISPLAY; }
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"$fdisplayb" { FL; return yD_FDISPLAYB; }
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"$fdisplayh" { FL; return yD_FDISPLAYH; }
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"$fdisplayo" { FL; return yD_FDISPLAYO; }
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"$feof" { FL; return yD_FEOF; }
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"$ferror" { FL; return yD_FERROR; }
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"$fflush" { FL; return yD_FFLUSH; }
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"$fgetc" { FL; return yD_FGETC; }
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"$fgets" { FL; return yD_FGETS; }
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"$finish" { FL; return yD_FINISH; }
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"$floor" { FL; return yD_FLOOR; }
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"$fopen" { FL; return yD_FOPEN; }
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"$fread" { FL; return yD_FREAD; }
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"$frewind" { FL; return yD_FREWIND; }
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"$fscanf" { FL; return yD_FSCANF; }
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"$fseek" { FL; return yD_FSEEK; }
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"$ftell" { FL; return yD_FTELL; }
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"$fullskew" { FL; return yaTIMINGSPEC; }
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"$fwrite" { FL; return yD_FWRITE; }
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"$fwriteb" { FL; return yD_FWRITEB; }
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"$fwriteh" { FL; return yD_FWRITEH; }
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"$fwriteo" { FL; return yD_FWRITEO; }
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"$hold" { FL; return yaTIMINGSPEC; }
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"$hypot" { FL; return yD_HYPOT; }
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"$itor" { FL; return yD_ITOR; }
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"$ln" { FL; return yD_LN; }
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"$log10" { FL; return yD_LOG10; }
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"$nochange" { FL; return yaTIMINGSPEC; }
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"$period" { FL; return yaTIMINGSPEC; }
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"$pow" { FL; return yD_POW; }
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"$printtimescale" { FL; return yD_PRINTTIMESCALE; }
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"$random" { FL; return yD_RANDOM; }
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"$readmemb" { FL; return yD_READMEMB; }
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"$readmemh" { FL; return yD_READMEMH; }
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"$realtime" { FL; return yD_REALTIME; }
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"$realtobits" { FL; return yD_REALTOBITS; }
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"$recovery" { FL; return yaTIMINGSPEC; }
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"$recrem" { FL; return yaTIMINGSPEC; }
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"$removal" { FL; return yaTIMINGSPEC; }
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"$rewind" { FL; return yD_REWIND; }
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"$rtoi" { FL; return yD_RTOI; }
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"$sampled" { FL; return yD_SAMPLED; }
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"$setup" { FL; return yaTIMINGSPEC; }
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"$setuphold" { FL; return yaTIMINGSPEC; }
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"$sformat" { FL; return yD_SFORMAT; }
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"$sformatf" { FL; return yD_SFORMATF; }
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"$shortrealtobits" { FL; return yD_SHORTREALTOBITS; }
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"$sin" { FL; return yD_SIN; }
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"$sinh" { FL; return yD_SINH; }
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"$skew" { FL; return yaTIMINGSPEC; }
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"$sqrt" { FL; return yD_SQRT; }
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"$sscanf" { FL; return yD_SSCANF; }
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"$stime" { FL; return yD_STIME; }
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"$stop" { FL; return yD_STOP; }
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"$swrite" { FL; return yD_SWRITE; }
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"$swriteb" { FL; return yD_SWRITEB; }
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"$swriteh" { FL; return yD_SWRITEH; }
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"$swriteo" { FL; return yD_SWRITEO; }
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"$system" { FL; return yD_SYSTEM; }
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"$tan" { FL; return yD_TAN; }
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"$tanh" { FL; return yD_TANH; }
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"$test$plusargs" { FL; return yD_TESTPLUSARGS; }
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"$time" { FL; return yD_TIME; }
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"$timeskew" { FL; return yaTIMINGSPEC; }
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"$timeformat" { FL; return yD_TIMEFORMAT; }
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"$typename" { FL; return yD_TYPENAME; }
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"$ungetc" { FL; return yD_UNGETC; }
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"$value$plusargs" { FL; return yD_VALUEPLUSARGS; }
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"$width" { FL; return yaTIMINGSPEC; }
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"$write" { FL; return yD_WRITE; }
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"$writeb" { FL; return yD_WRITEB; }
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"$writeh" { FL; return yD_WRITEH; }
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"$writeo" { FL; return yD_WRITEO; }
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"$writememh" { FL; return yD_WRITEMEMH; }
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/* Keywords */
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"always" { FL; return yALWAYS; }
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"and" { FL; return yAND; }
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"assign" { FL; return yASSIGN; }
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"begin" { FL; return yBEGIN; }
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"buf" { FL; return yBUF; }
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"bufif0" { FL; return yBUFIF0; }
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"bufif1" { FL; return yBUFIF1; }
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"case" { FL; return yCASE; }
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"casex" { FL; return yCASEX; }
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"casez" { FL; return yCASEZ; }
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"cmos" { FL; return yCMOS; }
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"deassign" { FL; return yDEASSIGN; }
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"default" { FL; return yDEFAULT; }
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"defparam" { FL; return yDEFPARAM; }
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"disable" { FL; return yDISABLE; }
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"edge" { FL; return yEDGE; }
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"else" { FL; return yELSE; }
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"end" { FL; return yEND; }
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"endcase" { FL; return yENDCASE; }
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"endfunction" { FL; return yENDFUNCTION; }
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"endmodule" { FL; return yENDMODULE; }
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"endprimitive" { FL; return yENDPRIMITIVE; }
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"endspecify" { FL; return yENDSPECIFY; }
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"endtable" { FL_FWD; yyerrorf("Syntax error: ENDTABLE outside of TABLE"); FL_BRK; }
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"endtask" { FL; return yENDTASK; }
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"event" { FL; return yEVENT; }
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"for" { FL; return yFOR; }
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"force" { FL; return yFORCE; }
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"foreach" { FL; return yFOREACH; }
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"forever" { FL; return yFOREVER; }
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"fork" { FL; return yFORK; }
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"function" { FL; return yFUNCTION; }
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"highz0" { FL; return ygenSTRENGTH; }
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"highz1" { FL; return ygenSTRENGTH; }
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"if" { FL; return yIF; }
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"initial" { FL; return yINITIAL; }
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"inout" { FL; return yINOUT; }
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"input" { FL; return yINPUT; }
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"integer" { FL; return yINTEGER; }
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"join" { FL; return yJOIN; }
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"large" { FL; return ygenSTRENGTH; }
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"macromodule" { FL; return yMODULE; }
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"medium" { FL; return ygenSTRENGTH; }
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"module" { FL; return yMODULE; }
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"nand" { FL; return yNAND; }
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"negedge" { FL; return yNEGEDGE; }
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"nmos" { FL; return yNMOS; }
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"nor" { FL; return yNOR; }
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"not" { FL; return yNOT; }
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"notif0" { FL; return yNOTIF0; }
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"notif1" { FL; return yNOTIF1; }
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"or" { FL; return yOR; }
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"output" { FL; return yOUTPUT; }
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"parameter" { FL; return yPARAMETER; }
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"pmos" { FL; return yPMOS; }
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"posedge" { FL; return yPOSEDGE; }
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"primitive" { FL; return yPRIMITIVE; }
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"pull0" { FL; return ygenSTRENGTH; }
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"pull1" { FL; return ygenSTRENGTH; }
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"pulldown" { FL; return yPULLDOWN; }
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"pullup" { FL; return yPULLUP; }
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"rcmos" { FL; return yRCMOS; }
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"real" { FL; return yREAL; }
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"realtime" { FL; return yREALTIME; }
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"reg" { FL; return yREG; }
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"release" { FL; return yRELEASE; }
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"repeat" { FL; return yREPEAT; }
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"rnmos" { FL; return yRNMOS; }
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"rpmos" { FL; return yRPMOS; }
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"rtran" { FL; return yRTRAN; }
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"rtranif0" { FL; return yRTRANIF0; }
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"rtranif1" { FL; return yRTRANIF1; }
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"scalared" { FL; return ySCALARED; }
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"small" { FL; return ygenSTRENGTH; }
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"specify" { FL; return ySPECIFY; }
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"specparam" { FL; return ySPECPARAM; }
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"strong0" { FL; return ygenSTRENGTH; }
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"strong1" { FL; return ygenSTRENGTH; }
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"supply0" { FL; return ySUPPLY0; }
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"supply1" { FL; return ySUPPLY1; }
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"table" { FL; yy_push_state(TABLE); return yTABLE; }
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"task" { FL; return yTASK; }
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"time" { FL; return yTIME; }
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"tran" { FL; return yTRAN; }
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"tranif0" { FL; return yTRANIF0; }
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"tranif1" { FL; return yTRANIF1; }
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"tri" { FL; return yTRI; }
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"tri0" { FL; return yTRI0; }
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"tri1" { FL; return yTRI1; }
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"triand" { FL; return yTRIAND; }
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"trior" { FL; return yTRIOR; }
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"trireg" { FL; return yTRIREG; }
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"vectored" { FL; return yVECTORED; }
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|
"wait" { FL; return yWAIT; }
|
|
"wand" { FL; return yWAND; }
|
|
"weak0" { FL; return ygenSTRENGTH; }
|
|
"weak1" { FL; return ygenSTRENGTH; }
|
|
"while" { FL; return yWHILE; }
|
|
"wire" { FL; return yWIRE; }
|
|
"wor" { FL; return yWOR; }
|
|
"xnor" { FL; return yXNOR; }
|
|
"xor" { FL; return yXOR; }
|
|
}
|
|
|
|
/* Verilog 2001 */
|
|
<V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
/* System Tasks */
|
|
"$signed" { FL; return yD_SIGNED; }
|
|
"$unsigned" { FL; return yD_UNSIGNED; }
|
|
/* Keywords */
|
|
"automatic" { FL; return yAUTOMATIC; }
|
|
"endgenerate" { FL; return yENDGENERATE; }
|
|
"generate" { FL; return yGENERATE; }
|
|
"genvar" { FL; return yGENVAR; }
|
|
"ifnone" { FL; return yaTIMINGSPEC; }
|
|
"localparam" { FL; return yLOCALPARAM; }
|
|
"noshowcancelled" { FL; return yaTIMINGSPEC; }
|
|
"pulsestyle_ondetect" { FL; return yaTIMINGSPEC; }
|
|
"pulsestyle_onevent" { FL; return yaTIMINGSPEC; }
|
|
"showcancelled" { FL; return yaTIMINGSPEC; }
|
|
"signed" { FL; return ySIGNED; }
|
|
"unsigned" { FL; return yUNSIGNED; }
|
|
/* Generic unsupported keywords */
|
|
"cell" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"config" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"design" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"endconfig" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"incdir" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"include" { FL_FWD; yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: %s", yytext); FL_BRK; }
|
|
"instance" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"liblist" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"library" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
"use" { ERROR_RSVD_WORD("Verilog 2001-config"); }
|
|
}
|
|
|
|
/* Verilog 2005 */
|
|
<V05,S05,S09,S12,S17,SAX>{
|
|
/* System Tasks */
|
|
"$clog2" { FL; return yD_CLOG2; }
|
|
/* Keywords */
|
|
"uwire" { FL; return yWIRE; }
|
|
}
|
|
|
|
/* System Verilog 2005 */
|
|
<S05,S09,S12,S17,SAX>{
|
|
/* System Tasks */
|
|
"$bits" { FL; return yD_BITS; }
|
|
"$countbits" { FL; return yD_COUNTBITS; }
|
|
"$countones" { FL; return yD_COUNTONES; }
|
|
"$dimensions" { FL; return yD_DIMENSIONS; }
|
|
"$error" { FL; return yD_ERROR; }
|
|
"$fatal" { FL; return yD_FATAL; }
|
|
"$high" { FL; return yD_HIGH; }
|
|
"$increment" { FL; return yD_INCREMENT; }
|
|
"$info" { FL; return yD_INFO; }
|
|
"$isunbounded" { FL; return yD_ISUNBOUNDED; }
|
|
"$isunknown" { FL; return yD_ISUNKNOWN; }
|
|
"$left" { FL; return yD_LEFT; }
|
|
"$low" { FL; return yD_LOW; }
|
|
"$onehot" { FL; return yD_ONEHOT; }
|
|
"$onehot0" { FL; return yD_ONEHOT0; }
|
|
"$past" { FL; return yD_PAST; }
|
|
"$right" { FL; return yD_RIGHT; }
|
|
"$root" { FL; return yD_ROOT; }
|
|
"$size" { FL; return yD_SIZE; }
|
|
"$unpacked_dimensions" { FL; return yD_UNPACKED_DIMENSIONS; }
|
|
"$warning" { FL; return yD_WARNING; }
|
|
/* SV2005 Keywords */
|
|
"$unit" { FL; return yD_UNIT; } /* Yes, a keyword, not task */
|
|
"alias" { FL; return yALIAS; }
|
|
"always_comb" { FL; return yALWAYS_COMB; }
|
|
"always_ff" { FL; return yALWAYS_FF; }
|
|
"always_latch" { FL; return yALWAYS_LATCH; }
|
|
"assert" { FL; return yASSERT; }
|
|
"assume" { FL; return yASSUME; }
|
|
"bind" { FL; return yBIND; }
|
|
"bit" { FL; return yBIT; }
|
|
"break" { FL; return yBREAK; }
|
|
"byte" { FL; return yBYTE; }
|
|
"chandle" { FL; return yCHANDLE; }
|
|
"class" { FL; return yCLASS; }
|
|
"clocking" { FL; return yCLOCKING; }
|
|
"const" { FL; return yCONST__LEX; }
|
|
"context" { FL; return yCONTEXT; }
|
|
"continue" { FL; return yCONTINUE; }
|
|
"cover" { FL; return yCOVER; }
|
|
"do" { FL; return yDO; }
|
|
"endclass" { FL; return yENDCLASS; }
|
|
"endclocking" { FL; return yENDCLOCKING; }
|
|
"endinterface" { FL; return yENDINTERFACE; }
|
|
"endpackage" { FL; return yENDPACKAGE; }
|
|
"endprogram" { FL; return yENDPROGRAM; }
|
|
"endproperty" { FL; return yENDPROPERTY; }
|
|
"enum" { FL; return yENUM; }
|
|
"export" { FL; return yEXPORT; }
|
|
"extends" { FL; return yEXTENDS; }
|
|
"extern" { FL; return yEXTERN; }
|
|
"final" { FL; return yFINAL; }
|
|
"forkjoin" { FL; return yFORKJOIN; }
|
|
"iff" { FL; return yIFF; }
|
|
"import" { FL; return yIMPORT; }
|
|
"inside" { FL; return yINSIDE; }
|
|
"int" { FL; return yINT; }
|
|
"interface" { FL; return yINTERFACE; }
|
|
"join_any" { FL; return yJOIN_ANY; }
|
|
"join_none" { FL; return yJOIN_NONE; }
|
|
"local" { FL; return yLOCAL__LEX; }
|
|
"logic" { FL; return yLOGIC; }
|
|
"longint" { FL; return yLONGINT; }
|
|
"modport" { FL; return yMODPORT; }
|
|
"new" { FL; return yNEW__LEX; }
|
|
"null" { FL; return yNULL; }
|
|
"package" { FL; return yPACKAGE; }
|
|
"packed" { FL; return yPACKED; }
|
|
"priority" { FL; return yPRIORITY; }
|
|
"program" { FL; return yPROGRAM; }
|
|
"property" { FL; return yPROPERTY; }
|
|
"protected" { FL; return yPROTECTED; }
|
|
"pure" { FL; return yPURE; }
|
|
"rand" { FL; return yRAND; }
|
|
"randc" { FL; return yRANDC; }
|
|
"randcase" { FL; return yRANDCASE; }
|
|
"ref" { FL; return yREF; }
|
|
"restrict" { FL; return yRESTRICT; }
|
|
"return" { FL; return yRETURN; }
|
|
"shortint" { FL; return ySHORTINT; }
|
|
"shortreal" { FL; return ySHORTREAL; }
|
|
"static" { FL; return ySTATIC__ETC; }
|
|
"string" { FL; return ySTRING; }
|
|
"struct" { FL; return ySTRUCT; }
|
|
"super" { FL; return ySUPER; }
|
|
"this" { FL; return yTHIS; }
|
|
"timeprecision" { FL; return yTIMEPRECISION; }
|
|
"timeunit" { FL; return yTIMEUNIT; }
|
|
"type" { FL; return yTYPE; }
|
|
"typedef" { FL; return yTYPEDEF; }
|
|
"union" { FL; return yUNION; }
|
|
"unique" { FL; return yUNIQUE; }
|
|
"var" { FL; return yVAR; }
|
|
"virtual" { FL; return yVIRTUAL__LEX; }
|
|
"void" { FL; return yVOID; }
|
|
/* Generic unsupported warnings */
|
|
/* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
|
|
"before" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"bins" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"binsof" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"constraint" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"covergroup" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"coverpoint" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"cross" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"dist" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"endgroup" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"endsequence" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"expect" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"first_match" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"ignore_bins" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"illegal_bins" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"intersect" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"matches" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"randomize" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"randsequence" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"sequence" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"solve" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"tagged" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"throughout" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"wait_order" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"wildcard" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"with" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
"within" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
|
|
}
|
|
|
|
/* SystemVerilog 2009 */
|
|
<S09,S12,S17,SAX>{
|
|
/* Keywords */
|
|
"global" { FL; return yGLOBAL__LEX; }
|
|
"unique0" { FL; return yUNIQUE0; }
|
|
/* Generic unsupported warnings */
|
|
"accept_on" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"checker" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"endchecker" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"eventually" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"implies" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"let" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"nexttime" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"reject_on" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"s_always" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"s_eventually" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"s_nexttime" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"s_until" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"s_until_with" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"strong" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"sync_accept_on" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"sync_reject_on" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"until" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"until_with" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"untyped" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
"weak" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
|
|
}
|
|
|
|
/* System Verilog 2012 */
|
|
<S12,S17,SAX>{
|
|
/* Keywords */
|
|
"implements" { FL; return yIMPLEMENTS; }
|
|
"interconnect" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
|
|
"nettype" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
|
|
"soft" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
|
|
}
|
|
|
|
/* System Verilog 2017 */
|
|
/* No new keywords */
|
|
|
|
/* Default PLI rule */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext, yyleng);
|
|
yylval.strp = PARSEP->newString(AstNode::encodeName(str));
|
|
FL; return yaD_PLI;
|
|
}
|
|
}
|
|
|
|
/************************************************************************/
|
|
/* AMS */
|
|
|
|
<VA5,SAX>{
|
|
/* Generic unsupported warnings */
|
|
"above" { ERROR_RSVD_WORD("AMS"); }
|
|
"abs" { ERROR_RSVD_WORD("AMS"); }
|
|
"absdelay" { ERROR_RSVD_WORD("AMS"); }
|
|
"abstol" { ERROR_RSVD_WORD("AMS"); }
|
|
"ac_stim" { ERROR_RSVD_WORD("AMS"); }
|
|
"access" { ERROR_RSVD_WORD("AMS"); }
|
|
"acos" { ERROR_RSVD_WORD("AMS"); }
|
|
"acosh" { ERROR_RSVD_WORD("AMS"); }
|
|
"aliasparam" { ERROR_RSVD_WORD("AMS"); }
|
|
"analog" { ERROR_RSVD_WORD("AMS"); }
|
|
"analysis" { ERROR_RSVD_WORD("AMS"); }
|
|
"asin" { FL; return yD_ASIN; }
|
|
"asinh" { FL; return yD_ASINH; }
|
|
"assert" { ERROR_RSVD_WORD("AMS"); }
|
|
"atan" { FL; return yD_ATAN; }
|
|
"atan2" { FL; return yD_ATAN2; }
|
|
"atanh" { FL; return yD_ATANH; }
|
|
"branch" { ERROR_RSVD_WORD("AMS"); }
|
|
"ceil" { FL; return yD_CEIL; }
|
|
"connect" { ERROR_RSVD_WORD("AMS"); }
|
|
"connectmodule" { ERROR_RSVD_WORD("AMS"); }
|
|
"connectrules" { ERROR_RSVD_WORD("AMS"); }
|
|
"continuous" { ERROR_RSVD_WORD("AMS"); }
|
|
"cos" { FL; return yD_COS; }
|
|
"cosh" { FL; return yD_COSH; }
|
|
"cross" { ERROR_RSVD_WORD("AMS"); }
|
|
"ddt" { ERROR_RSVD_WORD("AMS"); }
|
|
"ddt_nature" { ERROR_RSVD_WORD("AMS"); }
|
|
"ddx" { ERROR_RSVD_WORD("AMS"); }
|
|
"discipline" { ERROR_RSVD_WORD("AMS"); }
|
|
"discrete" { ERROR_RSVD_WORD("AMS"); }
|
|
"domain" { ERROR_RSVD_WORD("AMS"); }
|
|
"driver_update" { ERROR_RSVD_WORD("AMS"); }
|
|
"endconnectrules" { ERROR_RSVD_WORD("AMS"); }
|
|
"enddiscipline" { ERROR_RSVD_WORD("AMS"); }
|
|
"endnature" { ERROR_RSVD_WORD("AMS"); }
|
|
"endparamset" { ERROR_RSVD_WORD("AMS"); }
|
|
"exclude" { ERROR_RSVD_WORD("AMS"); }
|
|
"exp" { FL; return yD_EXP; }
|
|
"final_step" { ERROR_RSVD_WORD("AMS"); }
|
|
"flicker_noise" { ERROR_RSVD_WORD("AMS"); }
|
|
"floor" { FL; return yD_FLOOR; }
|
|
"flow" { ERROR_RSVD_WORD("AMS"); }
|
|
"from" { ERROR_RSVD_WORD("AMS"); }
|
|
"ground" { ERROR_RSVD_WORD("AMS"); }
|
|
"hypot" { FL; return yD_HYPOT; }
|
|
"idt" { ERROR_RSVD_WORD("AMS"); }
|
|
"idt_nature" { ERROR_RSVD_WORD("AMS"); }
|
|
"idtmod" { ERROR_RSVD_WORD("AMS"); }
|
|
"inf" { ERROR_RSVD_WORD("AMS"); }
|
|
"initial_step" { ERROR_RSVD_WORD("AMS"); }
|
|
"laplace_nd" { ERROR_RSVD_WORD("AMS"); }
|
|
"laplace_np" { ERROR_RSVD_WORD("AMS"); }
|
|
"laplace_zd" { ERROR_RSVD_WORD("AMS"); }
|
|
"laplace_zp" { ERROR_RSVD_WORD("AMS"); }
|
|
"last_crossing" { ERROR_RSVD_WORD("AMS"); }
|
|
"limexp" { ERROR_RSVD_WORD("AMS"); }
|
|
"ln" { FL; return yD_LN; }
|
|
"log" { FL; return yD_LOG10; }
|
|
"max" { ERROR_RSVD_WORD("AMS"); }
|
|
"merged" { ERROR_RSVD_WORD("AMS"); }
|
|
"min" { ERROR_RSVD_WORD("AMS"); }
|
|
"nature" { ERROR_RSVD_WORD("AMS"); }
|
|
"net_resolution" { ERROR_RSVD_WORD("AMS"); }
|
|
"noise_table" { ERROR_RSVD_WORD("AMS"); }
|
|
"paramset" { ERROR_RSVD_WORD("AMS"); }
|
|
"potential" { ERROR_RSVD_WORD("AMS"); }
|
|
"pow" { FL; return yD_POW; }
|
|
"resolveto" { ERROR_RSVD_WORD("AMS"); }
|
|
"sin" { FL; return yD_SIN; }
|
|
"sinh" { FL; return yD_SINH; }
|
|
"slew" { ERROR_RSVD_WORD("AMS"); }
|
|
"split" { ERROR_RSVD_WORD("AMS"); }
|
|
"sqrt" { FL; return yD_SQRT; }
|
|
"string" { FL; return ySTRING; }
|
|
"tan" { FL; return yD_TAN; }
|
|
"tanh" { FL; return yD_TANH; }
|
|
"timer" { ERROR_RSVD_WORD("AMS"); }
|
|
"transition" { ERROR_RSVD_WORD("AMS"); }
|
|
"units" { ERROR_RSVD_WORD("AMS"); }
|
|
"white_noise" { ERROR_RSVD_WORD("AMS"); }
|
|
"wreal" { FL; return yWREAL; }
|
|
"zi_nd" { ERROR_RSVD_WORD("AMS"); }
|
|
"zi_np" { ERROR_RSVD_WORD("AMS"); }
|
|
"zi_zd" { ERROR_RSVD_WORD("AMS"); }
|
|
"zi_zp" { ERROR_RSVD_WORD("AMS"); }
|
|
}
|
|
|
|
/************************************************************************/
|
|
/* Meta comments */
|
|
|
|
/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
"/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */
|
|
"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
|
|
"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
|
|
"/*verilator full_case*/" { FL; return yVL_FULL_CASE; }
|
|
"/*verilator inline_module*/" { FL; return yVL_INLINE_MODULE; }
|
|
"/*verilator isolate_assignments*/" { FL; return yVL_ISOLATE_ASSIGNMENTS; }
|
|
"/*verilator no_inline_module*/" { FL; return yVL_NO_INLINE_MODULE; }
|
|
"/*verilator no_inline_task*/" { FL; return yVL_NO_INLINE_TASK; }
|
|
"/*verilator parallel_case*/" { FL; return yVL_PARALLEL_CASE; }
|
|
"/*verilator public*/" { FL; return yVL_PUBLIC; }
|
|
"/*verilator public_flat*/" { FL; return yVL_PUBLIC_FLAT; }
|
|
"/*verilator public_flat_rd*/" { FL; return yVL_PUBLIC_FLAT_RD; }
|
|
"/*verilator public_flat_rw*/" { FL; return yVL_PUBLIC_FLAT_RW; } // The @(edge) is converted by the preproc
|
|
"/*verilator public_module*/" { FL; return yVL_PUBLIC_MODULE; }
|
|
"/*verilator split_var*/" { FL; return yVL_SPLIT_VAR; }
|
|
"/*verilator sc_clock*/" { FL; return yVL_CLOCK; }
|
|
"/*verilator clocker*/" { FL; return yVL_CLOCKER; }
|
|
"/*verilator no_clocker*/" { FL; return yVL_NO_CLOCKER; }
|
|
"/*verilator sc_bv*/" { FL; return yVL_SC_BV; }
|
|
"/*verilator sformat*/" { FL; return yVL_SFORMAT; }
|
|
"/*verilator systemc_clock*/" { FL; return yVL_CLOCK; }
|
|
"/*verilator tracing_off*/" { FL_FWD; PARSEP->fileline()->tracingOn(false); FL_BRK; }
|
|
"/*verilator tracing_on*/" { FL_FWD; PARSEP->fileline()->tracingOn(true); FL_BRK; }
|
|
"/*verilator coverage_off*/" { FL_FWD; PARSEP->fileline()->coverageOn(false); FL_BRK; }
|
|
"/*verilator coverage_on*/" { FL_FWD; PARSEP->fileline()->coverageOn(true); FL_BRK; }
|
|
"/*verilator lint_off"[^*]*"*/" { FL_FWD; PARSEP->verilatorCmtLint(yytext, true); FL_BRK; }
|
|
"/*verilator lint_on"[^*]*"*/" { FL_FWD; PARSEP->verilatorCmtLint(yytext, false); FL_BRK; }
|
|
"/*verilator lint_restore*/" { FL_FWD; PARSEP->verilatorCmtLintRestore(); FL_BRK; }
|
|
"/*verilator lint_save*/" { FL_FWD; PARSEP->verilatorCmtLintSave(); FL_BRK; }
|
|
"/*verilator tag"[^*]*"*/" { FL_FWD; PARSEP->tag(yytext); FL_BRK; }
|
|
|
|
"/**/" { FL_FWD; FL_BRK; }
|
|
"/*"[^*]+"*/" { FL_FWD; PARSEP->verilatorCmtBad(yytext); FL_BRK; }
|
|
}
|
|
|
|
/************************************************************************/
|
|
|
|
/* Single character operator thingies */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
"{" { FL; return yytext[0]; }
|
|
"}" { FL; return yytext[0]; }
|
|
"!" { FL; return yytext[0]; }
|
|
"#" { FL; return yytext[0]; }
|
|
"$" { FL; return yytext[0]; }
|
|
"%" { FL; return yytext[0]; }
|
|
"&" { FL; return yytext[0]; }
|
|
"(" { FL; return yytext[0]; }
|
|
")" { FL; return yytext[0]; }
|
|
"*" { FL; return yytext[0]; }
|
|
"+" { FL; return yytext[0]; }
|
|
"," { FL; return yytext[0]; }
|
|
"-" { FL; return yytext[0]; }
|
|
"." { FL; return yytext[0]; }
|
|
"/" { FL; return yytext[0]; }
|
|
":" { FL; return yytext[0]; }
|
|
";" { FL; return yytext[0]; }
|
|
"<" { FL; return yytext[0]; }
|
|
"=" { FL; return yytext[0]; }
|
|
">" { FL; return yytext[0]; }
|
|
"?" { FL; return yytext[0]; }
|
|
"@" { FL; return yytext[0]; }
|
|
"[" { FL; return yytext[0]; }
|
|
"]" { FL; return yytext[0]; }
|
|
"^" { FL; return yytext[0]; }
|
|
"|" { FL; return yytext[0]; }
|
|
"~" { FL; return yytext[0]; }
|
|
}
|
|
|
|
/************************************************************************/
|
|
/* Operators and multi-character symbols */
|
|
|
|
/* Verilog 1995 Operators */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
"&&" { FL; return yP_ANDAND; }
|
|
"||" { FL; return yP_OROR; }
|
|
"<=" { FL; return yP_LTE; }
|
|
">=" { FL; return yP_GTE; }
|
|
"<<" { FL; return yP_SLEFT; }
|
|
">>" { FL; return yP_SRIGHT; }
|
|
"==" { FL; return yP_EQUAL; }
|
|
"!=" { FL; return yP_NOTEQUAL; }
|
|
"===" { FL; return yP_CASEEQUAL; }
|
|
"!==" { FL; return yP_CASENOTEQUAL; }
|
|
"^~" { FL; return yP_XNOR; }
|
|
"~^" { FL; return yP_XNOR; }
|
|
"~&" { FL; return yP_NAND; }
|
|
"~|" { FL; return yP_NOR; }
|
|
"->" { FL; return yP_MINUSGT; }
|
|
"=>" { FL; return yP_EQGT; }
|
|
"*>" { FL; return yP_ASTGT; }
|
|
"&&&" { FL; return yP_ANDANDAND; }
|
|
}
|
|
|
|
/* Verilog 2001 Operators */
|
|
<V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
"<<<" { FL; return yP_SLEFT; }
|
|
">>>" { FL; return yP_SSRIGHT; }
|
|
"**" { FL; return yP_POW; }
|
|
"+:" { FL; return yP_PLUSCOLON; }
|
|
"-:" { FL; return yP_MINUSCOLON; }
|
|
".*" { FL; return yP_DOTSTAR; }
|
|
":+" { FL; yyless(1);
|
|
PARSEP->fileline()->v3warn(COLONPLUS, "Perhaps instead of ':+' the intent was '+:'?");
|
|
return ':'; }
|
|
}
|
|
|
|
/* SystemVerilog Operators */
|
|
<S05,S09,S12,S17,SAX>{
|
|
"'" { FL; return yP_TICK; }
|
|
"'{" { FL; return yP_TICKBRA; }
|
|
"==?" { FL; return yP_WILDEQUAL; }
|
|
"!=?" { FL; return yP_WILDNOTEQUAL; }
|
|
"++" { FL; return yP_PLUSPLUS; }
|
|
"--" { FL; return yP_MINUSMINUS; }
|
|
"+=" { FL; return yP_PLUSEQ; }
|
|
"-=" { FL; return yP_MINUSEQ; }
|
|
"*=" { FL; return yP_TIMESEQ; }
|
|
"/=" { FL; return yP_DIVEQ; }
|
|
"%=" { FL; return yP_MODEQ; }
|
|
"&=" { FL; return yP_ANDEQ; }
|
|
"|=" { FL; return yP_OREQ; }
|
|
"^=" { FL; return yP_XOREQ; }
|
|
"<<=" { FL; return yP_SLEFTEQ; }
|
|
">>=" { FL; return yP_SRIGHTEQ; }
|
|
"<<<=" { FL; return yP_SLEFTEQ; }
|
|
">>>=" { FL; return yP_SSRIGHTEQ; }
|
|
"->>" { FL; return yP_MINUSGTGT; }
|
|
"##" { FL; return yP_POUNDPOUND; }
|
|
"@@" { FL; return yP_ATAT; }
|
|
"::" { FL; return yP_COLONCOLON; }
|
|
":=" { FL; return yP_COLONEQ; }
|
|
":/"[^\/\*] { FL; return yP_COLONDIV; } /* : then comment is not ":/" */
|
|
"|->" { FL; return yP_ORMINUSGT; }
|
|
"|=>" { FL; return yP_OREQGT; }
|
|
/* Some simulators allow whitespace here. Grr */
|
|
"["{ws}*"*" { FL; return yP_BRASTAR; }
|
|
"["{ws}*"=" { FL; return yP_BRAEQ; }
|
|
"["{ws}*"->" { FL; return yP_BRAMINUSGT; }
|
|
}
|
|
|
|
/* SystemVerilog 2009 Operators */
|
|
<S09,S12,S17,SAX,VLT>{
|
|
"<->" { FL; return yP_LTMINUSGT; }
|
|
}
|
|
|
|
/* Identifiers and numbers */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
|
|
{escid} { FL; yylval.strp = PARSEP->newString
|
|
(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
|
|
return yaID__LEX;
|
|
}
|
|
{id} { FL; yylval.strp = PARSEP->newString(AstNode::encodeName(string(yytext)));
|
|
return yaID__LEX;
|
|
}
|
|
\"[^\"\\]*\" { FL; yylval.strp = PARSEP->newString(yytext+1, yyleng-2);
|
|
return yaSTRING;
|
|
}
|
|
\" { yy_push_state(STRING); yymore(); }
|
|
{vnum} {
|
|
/* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */
|
|
if (PARSEP->prevLexToken()=='#') {
|
|
int shortlen = 0;
|
|
while (isdigit(yytext[shortlen])) shortlen++;
|
|
if (shortlen) {
|
|
// Push rest past numbers for later parse
|
|
PARSEP->unputString(yytext+shortlen, yyleng-shortlen);
|
|
// Return is stuff before the tick
|
|
yyleng = shortlen;
|
|
yytext[yyleng] = '\0';
|
|
FL; yylval.nump = PARSEP->newNumber(yylval.fl, (char*)yytext);
|
|
return yaINTNUM;
|
|
}
|
|
}
|
|
FL; yylval.nump = PARSEP->newNumber(yylval. fl, (char*)yytext);
|
|
return yaINTNUM;
|
|
}
|
|
[0-9][_0-9]* {
|
|
FL; yylval.nump = PARSEP->newNumber(yylval.fl, (char*)yytext);
|
|
return yaINTNUM;
|
|
}
|
|
[0-9][_0-9]*(\.[_0-9]+)([eE][-+]?[_0-9]+)? {
|
|
FL; yylval.cdouble = PARSEP->parseDouble(yytext, yyleng);
|
|
return yaFLOATNUM;
|
|
}
|
|
[0-9][_0-9]*(\.[_0-9]+)?([eE][-+]?[_0-9]+) {
|
|
FL; yylval.cdouble = PARSEP->parseDouble(yytext, yyleng);
|
|
return yaFLOATNUM;
|
|
}
|
|
[0-9][_0-9]*(\.[_0-9]+)?(fs|ps|ns|us|ms|s) {
|
|
FL; yylval.cdouble = PARSEP->parseTimenum(yytext);
|
|
return yaTIMENUM;
|
|
}
|
|
1step {
|
|
FL; yylval.cdouble = 0; // Unsupported
|
|
return yaTIMENUM;
|
|
}
|
|
}
|
|
|
|
/************************************************************************/
|
|
/* STRINGS */
|
|
<STRING><<EOF>> { FL_FWD; yyerrorf("EOF in unterminated string");
|
|
yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
|
|
<STRING>{crnl} { FL_FWD; yyerrorf("Unterminated string"); FL_BRK; }
|
|
<STRING>\\{crnl} { yymore(); }
|
|
<STRING>\\. { yymore(); }
|
|
<STRING>\" { yy_pop_state();
|
|
FL; yylval.strp = PARSEP->newString(yytext+1, yyleng-2);
|
|
return yaSTRING; }
|
|
<STRING>{word} { yymore(); }
|
|
<STRING>. { yymore(); }
|
|
|
|
/************************************************************************/
|
|
/* Attributes */
|
|
<ATTRMODE>{crnl} { yymore(); }
|
|
<ATTRMODE>"*)" { FL_FWD; yy_pop_state(); FL_BRK; }
|
|
<ATTRMODE>{word} { yymore(); }
|
|
<ATTRMODE>. { yymore(); }
|
|
<ATTRMODE><<EOF>> { FL_FWD; yyerrorf("EOF in (*");
|
|
yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
|
|
|
|
/************************************************************************/
|
|
/* Attributes */
|
|
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
|
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */
|
|
}
|
|
|
|
/************************************************************************/
|
|
/* Tables */
|
|
<TABLE>\\{crnl} { yymore(); }
|
|
<TABLE>{crnl} { yymore(); }
|
|
<TABLE>";" { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLELINE; }
|
|
<TABLE>"endtable" { yy_pop_state(); FL; return yENDTABLE; }
|
|
<TABLE>"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->ppline(yytext); FL_BRK; }
|
|
<TABLE>. { yymore(); }
|
|
<TABLE><<EOF>> { FL_FWD; yyerrorf("EOF in TABLE");
|
|
yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
|
|
|
|
/************************************************************************/
|
|
/* Preprocessor */
|
|
/* Common for all SYSC header states */
|
|
/* OPTIMIZE: we return one per line, make it one for the entire block */
|
|
/* If add to this list also add to V3LanguageWords.h */
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
|
|
"`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`celldefine" { FL_FWD; PARSEP->inCellDefine(true); FL_BRK; }
|
|
"`default_decay_time"{ws}+[^\n\r]* { FL_FWD; FL_BRK; } // Verilog spec - delays only
|
|
"`default_nettype"{ws}+"wire" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); FL_BRK; }
|
|
"`default_nettype"{ws}+"none" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, false); FL_BRK; }
|
|
"`default_nettype"{ws}+[a-zA-Z0-9]* { FL_FWD; yyerrorf("Unsupported: `default_nettype of other than none or wire: %s", yytext); FL_BRK; }
|
|
"`default_trireg_strength"{ws}+[^\n\r]* { FL_FWD; yyerrorf("Unsupported: Verilog optional directive not implemented: %s", yytext); FL_BRK; }
|
|
"`delay_mode_distributed" { FL_FWD; FL_BRK; } // Verilog spec - delays only
|
|
"`delay_mode_path" { FL_FWD; FL_BRK; } // Verilog spec - delays only
|
|
"`delay_mode_unit" { FL_FWD; FL_BRK; } // Verilog spec - delays only
|
|
"`delay_mode_zero" { FL_FWD; FL_BRK; } // Verilog spec - delays only
|
|
"`disable_portfaults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`enable_portfaults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`endcelldefine" { FL_FWD; PARSEP->inCellDefine(false); FL_BRK; }
|
|
"`endprotect" { FL_FWD; FL_BRK; }
|
|
"`expand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`inline" { FL_FWD; FL_BRK; }
|
|
"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->ppline(yytext); FL_BRK; }
|
|
"`noaccelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`noexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`noremove_gatenames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`noremove_netnames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`nosuppress_faults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`nounconnected_drive" { FL_FWD; PARSEP->unconnectedDrive(VOptionBool::OPT_DEFAULT_FALSE); FL_BRK; }
|
|
"`portcoerce" { FL_FWD; FL_BRK; }
|
|
"`pragma"{ws}*[^\n\r]* { FL_FWD; FL_BRK; } // Verilog 2005
|
|
"`protect" { FL_FWD; FL_BRK; }
|
|
"`remove_gatenames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`remove_netnames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`resetall" { FL; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true);
|
|
return yaT_RESETALL; } // Rest handled by preproc
|
|
"`suppress_faults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
"`timescale"{ws}+[^\n\r]* { FL_FWD; PARSEP->timescalePreproc(PARSEP->fileline(),
|
|
yytext + strlen("`timescale"));
|
|
FL_BRK; }
|
|
"`unconnected_drive"{ws}+"pull0" { FL_FWD; PARSEP->unconnectedDrive(VOptionBool::OPT_FALSE); FL_BRK; }
|
|
"`unconnected_drive"{ws}+"pull1" { FL_FWD; PARSEP->unconnectedDrive(VOptionBool::OPT_TRUE); FL_BRK; }
|
|
"`unconnected_drive" { FL_FWD; yyerrorf("Bad `unconnected_drive syntax"); FL_BRK; }
|
|
"`uselib"{ws}+[^\n\r]* { FL_FWD; FL_BRK; } // Verilog-XL compatibility
|
|
|
|
/* See also setLanguage below */
|
|
"`begin_keywords"[ \t]*\"1364-1995\" { FL_FWD; yy_push_state(V95); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1364-2001\" { FL_FWD; yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1364-2005\" { FL_FWD; yy_push_state(V05); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { FL_FWD; yy_push_state(VA5); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1800-2005\" { FL_FWD; yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1800-2009\" { FL_FWD; yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1800-2012\" { FL_FWD; yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1800-2017\" { FL_FWD; yy_push_state(S17); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
|
|
"`begin_keywords"[ \t]*\"1800[+]VAMS\" { FL_FWD; yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } /*Latest SV*/
|
|
"`end_keywords" { FL_FWD; yy_pop_state();
|
|
if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block");
|
|
FL_BRK; }
|
|
|
|
/* Verilator */
|
|
"`systemc_ctor" { FL_FWD; BEGIN SYSCCTOR; FL_BRK; }
|
|
"`systemc_dtor" { FL_FWD; BEGIN SYSCDTOR; FL_BRK; }
|
|
"`systemc_header" { FL_FWD; BEGIN SYSCHDR; FL_BRK; }
|
|
"`systemc_imp_header" { FL_FWD; BEGIN SYSCIMPH; FL_BRK; }
|
|
"`systemc_implementation" { FL_FWD; BEGIN SYSCIMP; FL_BRK; }
|
|
"`systemc_interface" { FL_FWD; BEGIN SYSCINT; FL_BRK; }
|
|
"`verilator_config" { FL_FWD; BEGIN VLT; FL_BRK; }
|
|
"`verilog" { FL_FWD; BEGIN PARSEP->lastVerilogState(); FL_BRK; }
|
|
|
|
/* Errors */
|
|
"<<<<<<<"[^\n\r]* { FL_FWD; yyerrorf("version control conflict marker in file"); FL_BRK; }
|
|
"======="[^\n\r]* { FL_FWD; yyerrorf("version control conflict marker in file"); FL_BRK; }
|
|
">>>>>>>"[^\n\r]* { FL_FWD; yyerrorf("version control conflict marker in file"); FL_BRK; }
|
|
|
|
/* If add to this list also add to V3LanguageWords.h */
|
|
}
|
|
|
|
<SYSCHDR>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCHDR; }
|
|
<SYSCINT>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCINT; }
|
|
<SYSCIMP>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCIMP; }
|
|
<SYSCIMPH>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCIMPH; }
|
|
<SYSCCTOR>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCCTOR; }
|
|
<SYSCDTOR>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCDTOR; }
|
|
<IGNORE>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL_FWD; FL_BRK; }
|
|
|
|
/* Pick up text-type data */
|
|
<SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
|
|
{wsnr}* { yymore(); }
|
|
{crnl} { yymore(); }
|
|
}
|
|
|
|
/************************************************************************/
|
|
/* Default rules - leave last */
|
|
|
|
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
|
|
"`"[a-zA-Z_0-9]+ { FL_FWD; PARSEP->errorPreprocDirective(yytext); FL_BRK; }
|
|
"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */
|
|
. { FL; return yytext[0]; } /* return single char ops. */
|
|
}
|
|
|
|
/* Catch all - absolutely last */
|
|
<*>.|\n { FL_FWD; yyerrorf("Missing verilog.l rule: Default rule invoked in state %d: %s", YY_START, yytext); FL_BRK; }
|
|
%%
|
|
// Avoid code here as cl format misindents
|
|
// For implementation functions see V3ParseImp.cpp
|
|
|
|
int V3ParseImp::stateVerilogRecent() { return STATE_VERILOG_RECENT; }
|