forked from github/verilator
18 lines
343 B
Systemverilog
18 lines
343 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Julien Margetts.
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module t (/*AUTOARG*/ a, b, o);
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input a;
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input b;
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output reg o;
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always_latch @(a or b)
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if (a)
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o <= b;
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else
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o <= ~b;
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endmodule
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