forked from github/verilator
31 lines
653 B
Systemverilog
31 lines
653 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module test(
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/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cnt = 32'h12345678;
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int cyc = 0;
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always @(posedge clk) begin
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if (cyc > 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end else begin
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cyc <= cyc + 1;
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cnt <= cnt + 1;
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$write("%08x\n", {16'h0, cnt[15: 0]});
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$write("%08x\n", {16'h0, cnt[31:16]});
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end
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end
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endmodule
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