forked from github/verilator
31 lines
716 B
Systemverilog
31 lines
716 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire[3:0] #4 val1 = cyc;
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wire[3:0] #4 val2;
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reg[3:0] cyc = 0;
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assign #4 val2 = cyc;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc=%0d, val1=%0d, val2=%0d\n", $time, cyc, val1, val2);
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`endif
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if (cyc >= 4 && val1 != cyc-1 && val2 != cyc-3) $stop;
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if (cyc == 15) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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