forked from github/verilator
31 lines
572 B
Systemverilog
31 lines
572 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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timeunit 10ps;
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timeprecision 10ps;
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task show;
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$printtimescale;
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endtask
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module from_unit;
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task show;
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$printtimescale;
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endtask
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endmodule
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module t;
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from_unit from_unit();
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timeunit 100ps;
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initial begin
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show();
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from_unit.show();
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$printtimescale;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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