forked from github/verilator
103 lines
2.3 KiB
Systemverilog
103 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [3:0] in;
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tri [3:0] bus = in;
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int never_driven;
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int never_forced;
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task force_bus;
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force bus[1:0] = 2'b10;
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endtask
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task release_bus;
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release bus;
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endtask
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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in <= 4'b0101;
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end
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else if (cyc == 1) begin
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`checkh(in, 4'b0101);
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end
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// Check forces with no driver
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if (cyc == 1) begin
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force never_driven = 32'h888;
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end
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else if (cyc == 2) begin
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`checkh(never_driven, 32'h888);
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end
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// Check release with no force
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else if (cyc == 10) begin
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never_forced <= 5432;
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end
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else if (cyc == 11) begin
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`checkh(never_forced, 5432);
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end
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else if (cyc == 12) begin
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release never_forced; // no-op
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end
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else if (cyc == 13) begin
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`checkh(never_forced, 5432);
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end
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//
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// bus
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else if (cyc == 10) begin
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`checkh(bus, 4'b0101);
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force bus = 4'b0111;
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end
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else if (cyc == 11) begin
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`checkh(bus, 4'b0111);
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force bus = 4'b1111;
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end
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else if (cyc == 12) begin
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`checkh(bus, 4'b1111);
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release bus;
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end
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else if (cyc == 13) begin
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`checkh(bus, 4'b0101);
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end
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else if (cyc == 20) begin
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force_bus();
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end
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else if (cyc == 21) begin
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`checkh(bus, 4'b0110);
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end
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else if (cyc == 22) begin
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release bus[0];
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end
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else if (cyc == 23) begin
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`checkh(bus, 4'b0111);
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release_bus();
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end
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else if (cyc == 24) begin
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`checkh(in, 4'b0101);
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`checkh(bus, 4'b0101);
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end
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//
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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