forked from github/verilator
100 lines
2.4 KiB
Verilog
100 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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wire one = '1;
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wire z0 = 'z;
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wire z1 = 'z;
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wire z2 = 'z;
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wire z3 = 'z;
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// verilator lint_off PINMISSING
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t_tri0 tri0a (); // Error/warning
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t_tri0 tri0b (.tn());
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t_tri0 tri0z (.tn(z0));
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t_tri0 #(.EXPECT(1'b0)) tri0c (.tn(1'b0));
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t_tri0 #(.EXPECT(1'b1)) tri0d (.tn(1'b1)); // Warning would be reasonable given tri0 connect
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t_tri0 #(.EXPECT(1'b0)) tri0e (.tn(~one));
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t_tri0 #(.EXPECT(1'b1)) tri0f (.tn(one));
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t_tri1 tri1a ();
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t_tri1 tri1b (.tn());
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t_tri1 tri1z (.tn(z1));
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t_tri1 #(.EXPECT(1'b0)) tri1c (.tn(1'b0)); // Warning would be reasonable given tri1 connect
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t_tri1 #(.EXPECT(1'b1)) tri1d (.tn(1'b1));
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t_tri1 #(.EXPECT(1'b0)) tri1e (.tn(~one));
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t_tri1 #(.EXPECT(1'b1)) tri1f (.tn(one));
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t_tri2 tri2a ();
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t_tri2 tri2b (.tn());
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t_tri2 tri2z (.tn(z2));
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t_tri2 #(.EXPECT(1'b0)) tri2c (.tn(1'b0));
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t_tri2 #(.EXPECT(1'b1)) tri2d (.tn(1'b1));
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t_tri2 #(.EXPECT(1'b0)) tri2e (.tn(~one));
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t_tri2 #(.EXPECT(1'b1)) tri2f (.tn(one));
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t_tri3 tri3a ();
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t_tri3 tri3b (.tn());
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t_tri3 tri3z (.tn(z3));
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t_tri3 #(.EXPECT(1'b0)) tri3c (.tn(1'b0));
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t_tri3 #(.EXPECT(1'b1)) tri3d (.tn(1'b1));
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t_tri3 #(.EXPECT(1'b0)) tri3e (.tn(~one));
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t_tri3 #(.EXPECT(1'b1)) tri3f (.tn(one));
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// verilator lint_on PINMISSING
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t_tri0
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#(parameter EXPECT=1'b0)
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(tn);
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input tn; // Illegal to be inout; spec requires net connection to any inout
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tri0 tn;
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wire clk = t.clk;
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always @(posedge clk) if (tn !== EXPECT) $stop;
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endmodule
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module t_tri1
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#(parameter EXPECT=1'b1)
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(tn);
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input tn;
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tri1 tn;
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wire clk = t.clk;
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always @(posedge clk) if (tn !== EXPECT) $stop;
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endmodule
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module t_tri2
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#(parameter EXPECT=1'b0)
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(tn);
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input tn;
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pulldown(tn);
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wire clk = t.clk;
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always @(posedge clk) if (tn !== EXPECT) $stop;
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endmodule
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module t_tri3
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#(parameter EXPECT=1'b1)
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(tn);
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input tn;
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pullup(tn);
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wire clk = t.clk;
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always @(posedge clk) if (tn !== EXPECT) $stop;
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endmodule
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