forked from github/verilator
22 lines
1.2 KiB
Plaintext
22 lines
1.2 KiB
Plaintext
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
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: ... In instance t
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25 | w = '0;
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| ^
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
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: ... In instance t
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26 | o = '0;
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| ^
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
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: ... In instance t
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27 | oa = '0;
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| ^~
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo'
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: ... In instance t
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28 | wo = '0;
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| ^~
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa'
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: ... In instance t
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29 | woa = '0;
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| ^~~
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%Error: Exiting due to
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