forked from github/verilator
21 lines
417 B
Systemverilog
21 lines
417 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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int q[$];
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int assoc[int];
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int dyn[];
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bit m;
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initial begin
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m = (10 inside {q});
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m = (10 inside {assoc});
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m = (10 inside {dyn});
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end
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endmodule
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