forked from github/verilator
20 lines
432 B
Systemverilog
20 lines
432 B
Systemverilog
// DESCRIPTION: Verilator: Test of select from constant
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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task foo(inout sig);
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sig = '1;
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endtask
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reg [3:0] bus_we_select_from;
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initial begin
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foo(bus_we_select_from[2]); // Will get TASKNSVAR error
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end
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endmodule
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