forked from github/verilator
20 lines
541 B
Systemverilog
20 lines
541 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t;
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// bug1081 - We don't use VPI, just need SC with VPI
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initial begin
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$write("%0t: Hello\n", $time);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : t
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