forked from github/verilator
5d98035170
cint.mainInt(nodep) walks the tree and populates m_ctorVarsVec. Reuse EmitCImp cint for the slow mainImp() emition steps to make sure we emit constructor calls to setup SystemC sc_module names.
12 lines
266 B
Systemverilog
12 lines
266 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Edgar E. Iglesias.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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clk
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);
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input clk;
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endmodule
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