forked from github/verilator
26 lines
517 B
Systemverilog
26 lines
517 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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z, z2, r,
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// Inputs
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a, b
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);
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input signed [17*32 : 0] a;
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input signed [17*32 : 0] b;
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output signed [17*32 : 0] z;
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output signed [17*32 : 0] z2;
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output real r;
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assign z = a * b;
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assign z2 = a ** 3;
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assign r = real'(a);
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endmodule
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