forked from github/verilator
22 lines
394 B
Systemverilog
22 lines
394 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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o,
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// Inputs
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clk, i
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);
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input clk;
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input [31:0] i;
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output [31:0] o;
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assign o = i << 64'h01234567_89abcdef;
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endmodule
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