forked from github/verilator
26 lines
536 B
Systemverilog
26 lines
536 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2006 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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sub sub ();
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input clk;
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integer cyc=1;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==2) begin
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// Not $finish; as we don't want a message to scroll by
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$c("Verilated::gotFinish(true);");
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end
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end
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endmodule
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module sub;
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/* verilator public_module */
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endmodule
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