forked from github/verilator
28 lines
706 B
Perl
Executable File
28 lines
706 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_clk_latch.v");
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my $fail = $Self->{vlt_all};
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compile(
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v_flags2 => ['+define+EDGE_DETECT_STYLE'],
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fails => $fail,
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);
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execute(
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check_finished => !$fail,
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) if !$fail;
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ok(1);
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1;
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