forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
38 lines
631 B
Verilog
38 lines
631 B
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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input i1;
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input [7:0] i8;
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input [15:0] i16;
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input [31:0] i32;
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input [63:0] i64;
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input [64:0] i65;
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output o1;
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output [7:0] o8;
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output [15:0] o16;
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output [31:0] o32;
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output [63:0] o64;
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output [64:0] o65;
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always @ (posedge clk) begin
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o1 <= i1;
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o8 <= i8;
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o16 <= i16;
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o32 <= i32;
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o64 <= i64;
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o65 <= i65;
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end
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endmodule
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