forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
18 lines
450 B
Verilog
18 lines
450 B
Verilog
`line 2 "inc3_a_filename_from_line_directive" 0
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// DESCRIPTION: Verilog::Preproc: Example source code
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2000-2005 by Wilson Snyder.
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`ifndef _EXAMPLE_INC2_V_
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`define _EXAMPLE_INC2_V_ 1
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`define _EMPTY
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// FOO
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At file `__FILE__ line `__LINE__
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`else
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`error "INC2 File already included once"
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`endif // guard
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`ifdef not_defined
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`include "NotToBeInced.v"
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`endif
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