forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
23 lines
470 B
Verilog
23 lines
470 B
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish
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// on success, or $stop.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here**
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module t (/*AUTOARG*/);
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wire foo;
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wire bar;
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// Oh dear.
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assign foo = bar;
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assign bar = foo;
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endmodule
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