forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
27 lines
604 B
Verilog
27 lines
604 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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`define RegDel 1
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module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal);
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input Clk;
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input [1:0] SlotIdx;
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input BitToChange;
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input BitVal;
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input [1:0] SlotToReturn;
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output [1:0] OutputVal;
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reg [1:0] Array[0:2];
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always @(posedge Clk)
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begin
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Array[SlotIdx][BitToChange] <= #`RegDel BitVal;
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OutputVal = Array[SlotToReturn];
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end
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endmodule
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