forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
27 lines
617 B
Verilog
27 lines
617 B
Verilog
// $Id:$
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2003 by Wilson Snyder.
|
|
|
|
module t (/*AUTOARG*/);
|
|
|
|
reg [3:0] a;
|
|
reg [99:0] x;
|
|
|
|
initial begin
|
|
a = 4'b010x;
|
|
if (a[3:2] !== 2'b01) $stop;
|
|
if (|a !== 1'b1) $stop;
|
|
if (&a !== 1'b0) $stop;
|
|
x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
|
|
endmodule
|
|
|
|
// Local Variables:
|
|
// compile-command: "./vlint __FILE__"
|
|
// End:
|