forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
50 lines
999 B
Verilog
50 lines
999 B
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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wire [17:10] bitout;
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reg [7:0] allbits;
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reg [15:0] onebit;
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sub sub [7:0] (allbits, onebit, bitout);
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always @ (posedge clk) begin
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//$write("%x\n", bitout);
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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allbits <= 8'hac;
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onebit <= 16'hc01a;
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end
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if (cyc==2) begin
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if (bitout !== 8'h07) $stop;
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allbits <= 8'hca;
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onebit <= 16'h1f01;
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end
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if (cyc==3) begin
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if (bitout !== 8'h41) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
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wire bitout = (^ onebit) ^ (^ allbits);
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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