forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
24 lines
437 B
Verilog
24 lines
437 B
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg [3:0] out;
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reg [38:0] in;
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initial begin
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in = 39'h0;
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out = MUX (in);
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$write("bad widths %x", out);
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end
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function [31:0] MUX;
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input [39:0] XX ;
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begin
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MUX = XX[39:8];
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end
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endfunction
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endmodule
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