forked from github/verilator
89 lines
2.2 KiB
Systemverilog
89 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork.
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// SPDX-License-Identifier: CC0-1.0
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interface intf;
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logic logic_in_intf;
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modport source(output logic_in_intf);
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modport sink(input logic_in_intf);
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endinterface
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module modify_interface
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(
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input logic value,
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intf.source intf_inst
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);
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export "DPI-C" function set_value;
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function void set_value(int value_in);
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intf_inst.logic_in_intf = value_in[0];
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endfunction
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assign intf_inst.logic_in_intf = value;
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endmodule
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function integer return_3();
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return 3;
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endfunction
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module t
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#(
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parameter N = 6
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)();
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intf ifs[N-1:0] ();
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logic [N-1:0] data;
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assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1};
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export "DPI-C" function set_data;
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function void set_data(int data_in);
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data = data_in[N-1:0];
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endfunction
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export "DPI-C" function set_intf_data;
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function void set_intf_data(int data_in);
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ifs[0].logic_in_intf = data_in[0];
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ifs[1].logic_in_intf = data_in[1];
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ifs[2].logic_in_intf = data_in[2];
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ifs[3].logic_in_intf = data_in[3];
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ifs[4].logic_in_intf = data_in[4];
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ifs[5].logic_in_intf = data_in[5];
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endfunction
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generate
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genvar i;
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for (i = 0;i < 3; i++) begin
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assign ifs[i].logic_in_intf = data[i];
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end
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endgenerate
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modify_interface m3 (
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.value(data[return_3()]),
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.intf_inst(ifs[return_3()]));
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modify_interface m4 (
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.value(data[4]),
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.intf_inst(ifs[4]));
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modify_interface m5 (
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.value(~ifs[4].logic_in_intf),
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.intf_inst(ifs[5]));
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generate
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genvar j;
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for (j = 0;j < N-1; j++) begin
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initial begin
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if (ifs[j].logic_in_intf != data[j])
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$display("!!!ERROR!!! ifs[%0d].logic_in_intf (%0d) != data[%0d] (%0d)",
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j, ifs[j].logic_in_intf, j, data[j]);
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end
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end
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endgenerate
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initial begin
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if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $display("BAD");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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