forked from github/verilator
48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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reg [31:0] dly0;
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wire [31:0] dly1;
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wire [31:0] dly2 = dly1 + 32'h1;
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typedef struct packed { int dly; } dly_s_t;
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dly_s_t dly_s;
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assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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dly0 <= #0 32'h11;
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end
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else if (cyc == 2) begin
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dly0 <= #0.12 dly0 + 32'h12;
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end
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else if (cyc == 3) begin
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if (dly0 !== 32'h23) $stop;
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if (dly2 !== 32'h25) $stop;
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end
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else if (cyc == 4) begin
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dly_s.dly = 55;
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dly0 <= #(dly_s.dly) 32'h55;
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//dly0 <= # dly_s.dly 32'h55; // Unsupported, issue-2410
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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#100 $finish;
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end
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end
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endmodule
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