forked from github/verilator
23 lines
710 B
Plaintext
23 lines
710 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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public -module "t" @(posedge clk)
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// only signals/functions/tasks
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isolate_assignments -module "t"
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// -match not supported
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tracing_off --file "*" -match "nothing"
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// -scope not supported
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lint_off --rule UNOPTFLAT -scope "top*"
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lint_off --rule UNOPTFLAT -scope "top*" -levels 0
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lint_on --rule UNOPTFLAT -scope "top*"
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lint_on --rule UNOPTFLAT -scope "top*" -levels 0
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// bad, --module missing
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forceable -module "" -var "net_*"
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// bad, --var missing
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forceable -module "top" -var ""
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