forked from github/verilator
34 lines
796 B
Systemverilog
34 lines
796 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk1, clk2);
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input wire clk1;
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input wire clk2;
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wire a;
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nor (pull0, weak1) n1(a, 0, 0);
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assign (strong0, weak1) a = 0;
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wire [1:0] b;
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assign (weak0, supply1) b = '1;
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assign b = clk1 ? '0 : 'z;
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wire c = 1;
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assign (weak0, pull1) c = clk1 & clk2;
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always begin
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if (!a && b === '1 && c) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Error: a = %b, b = %b, c = %b ", a, b, c);
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$write("expected: a = 0, b = 11, c = 1\n");
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$stop;
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end
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end
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endmodule
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