forked from github/verilator
708abe0dd1
This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
101 lines
2.5 KiB
C++
101 lines
2.5 KiB
C++
// DESCRIPTION: Verilator: Verilog Test
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//
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// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// clang-format off
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#include "verilatedos.h"
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#include VM_PREFIX_INCLUDE
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#include "Vt_trace_two_b.h"
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#include "verilated.h"
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#ifdef TEST_HDR_TRACE
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# ifdef TEST_FST
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# include "verilated_fst_c.h"
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# else
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# include "verilated_vcd_c.h"
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# endif
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#endif
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// clang-format on
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// Compile in place
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#include "Vt_trace_two_b.cpp"
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#include "Vt_trace_two_b__Syms.cpp"
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#include "Vt_trace_two_b___024root.cpp"
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#include "Vt_trace_two_b___024root__Slow.cpp"
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#include "Vt_trace_two_b__Trace.cpp"
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#include "Vt_trace_two_b__Trace__Slow.cpp"
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VM_PREFIX* ap;
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Vt_trace_two_b* bp;
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vluint64_t main_time = 0;
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double sc_time_stamp() { return main_time; }
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int main(int argc, char** argv, char** env) {
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vluint64_t sim_time = 1100;
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Verilated::commandArgs(argc, argv);
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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srand48(5);
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ap = new VM_PREFIX("topa");
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bp = new Vt_trace_two_b("topb");
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// clang-format off
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#ifdef TEST_HDR_TRACE
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Verilated::traceEverOn(true);
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# ifdef TEST_FST
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VerilatedFstC* tfp = new VerilatedFstC;
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ap->trace(tfp, 99);
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bp->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.fst");
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# else
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VerilatedVcdC* tfp = new VerilatedVcdC;
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ap->trace(tfp, 99);
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bp->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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# endif
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#endif
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// clang-format on
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#ifdef TEST_HDR_TRACE
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ap->eval_step();
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bp->eval_step();
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ap->eval_end_step();
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bp->eval_end_step();
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if (tfp) tfp->dump(main_time);
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#endif
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{
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ap->clk = false;
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main_time += 10;
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}
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while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
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ap->clk = !ap->clk;
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bp->clk = ap->clk;
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ap->eval_step();
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bp->eval_step();
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ap->eval_end_step();
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bp->eval_end_step();
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#ifdef TEST_HDR_TRACE
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if (tfp) tfp->dump(main_time);
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#endif
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main_time += 5;
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}
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if (!Verilated::gotFinish()) {
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vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
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}
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ap->final();
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bp->final();
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#ifdef TEST_HDR_TRACE
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if (tfp) tfp->close();
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VL_DO_DANGLING(delete tfp, tfp);
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#endif
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VL_DO_DANGLING(delete ap, ap);
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VL_DO_DANGLING(delete bp, bp);
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return 0;
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}
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