forked from github/verilator
27 lines
568 B
Systemverilog
27 lines
568 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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state,
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// Inputs
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clk
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);
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input clk;
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// Gave "Internal Error: V3Broken.cpp:: Broken link in node"
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output [1:0] state;
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reg [1:0] state = 2'b11;
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always @ (posedge clk) begin
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state <= state;
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end
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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