forked from github/verilator
d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
77 lines
1.6 KiB
Plaintext
77 lines
1.6 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Fri Jun 22 19:27:45 2018
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$end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 / clk $end
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$scope module t $end
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$var wire 32 % c1_count [31:0] $end
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$var wire 1 # c1_start $end
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$var wire 32 ( c3_count [31:0] $end
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$var wire 1 ' c3_start $end
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$var wire 1 / clk $end
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$var wire 8 $ cyc [7:0] $end
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$var wire 32 & s2_count [31:0] $end
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$var wire 1 # s2_start $end
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$scope module c1 $end
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$var wire 32 % count [31:0] $end
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$var wire 32 * runner [31:0] $end
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$var wire 32 ) runnerm1 [31:0] $end
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$var wire 1 # start $end
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$upscope $end
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$scope module c3 $end
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$var wire 32 ( count [31:0] $end
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$var wire 32 . runner [31:0] $end
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$var wire 32 - runnerm1 [31:0] $end
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$var wire 1 ' start $end
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$upscope $end
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$scope module s2 $end
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$var wire 32 & count [31:0] $end
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$var wire 32 , runner [31:0] $end
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$var wire 32 + runnerm1 [31:0] $end
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$var wire 1 # start $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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0#
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b00000000 $
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b00000000000000000000000000000000 %
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b00000000000000000000000000000000 &
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0'
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b00000000000000000000000000000000 (
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b11111111111111111111111111111111 )
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b00000000000000000000000000000000 *
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b11111111111111111111111111111111 +
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b00000000000000000000000000000000 ,
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b11111111111111111111111111111111 -
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b00000000000000000000000000000000 .
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0/
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#10
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b00000001 $
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1/
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#15
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0/
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#20
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1#
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b00000010 $
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b00000000000000000000000000000011 %
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b00000000000000000000000000000011 &
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1'
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b00000000000000000000000000000101 (
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1/
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#25
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0/
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#30
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b00000011 $
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1/
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#35
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0/
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#40
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b00000100 $
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1/
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