forked from github/verilator
708abe0dd1
This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
247 lines
7.6 KiB
Plaintext
247 lines
7.6 KiB
Plaintext
module Vt_debug_emitv___024root;
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input logic clk;
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input logic in;
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signed int [31:0] t.array[0:2];
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logic [15:0] t.pubflat;
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logic [15:0] t.pubflat_r;
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signed int [31:0] t.fd;
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signed int [31:0] t.i;
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signed int [31:0] t.cyc;
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signed int [31:0] t.fo;
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signed int [31:0] t.sum;
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signed real t.r;
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string t.str;
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signed int [31:0] t._Vpast_0_0;
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signed int [31:0] t._Vpast_1_0;
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signed int [31:0] t.unnamedblk3.i;
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@(*)@([settle])@([initial])@(posedge clk)@(negedge
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clk)always @(
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*)@(
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[settle])@(
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[initial])@(
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posedge
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clk)@(
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negedge
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clk) begin
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$display("stmt");
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end
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always @([settle])@([initial])@(posedge clk)@(negedge
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clk) begin
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$display("stmt");
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end
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initial begin
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// Function: f
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$write("stmt\nstmt 0 99\n");
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// Function: t
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$display("stmt");
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// Function: f
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$write("stmt\nstmt 1 -1\n");
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// Function: t
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$display("stmt");
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// Function: f
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$display("stmt");
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$display("stmt 2 -2");
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// Function: t
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$display("stmt");
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$display("stmt");
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end
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???? // CFUNC '_final_TOP'
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$display("stmt");
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always @(posedge clk)@(negedge clk) begin
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$display("posedge clk");
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end
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t.pubflat_r <= t.pubflat;
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end
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t.cyc <= (32'sh1 + t.cyc);
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__Vdly__t.r <= (0.01 + t.r);
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t.fo = t.cyc;
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// Function: inc
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__Vtask_t.sub.inc__2__i = t.fo;
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__Vtask_t.sub.inc__2__o = (32'h1 + __Vtask_t.sub.inc__2__i[31:1]);
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t.sum = __Vtask_t.sub.inc__2__o;
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// Function: f
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__Vfunc_t.sub.f__3__v = t.sum;
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begin : label0
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begin : label0
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if ((32'sh0 == __Vfunc_t.sub.f__3__v)) begin
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__Vfunc_t.sub.f__3__Vfuncout = 32'sh21;
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disable label0;
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end
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__Vfunc_t.sub.f__3__Vfuncout = (32'h1
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+ __Vfunc_t.sub.f__3__v[2]);
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disable label0;
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end
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end
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t.sum = __Vfunc_t.sub.f__3__Vfuncout;
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$display("[%0t] sum = %~", $timet.sum, t.sum);
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$display("a?= %d", ($c(32'sh1) ? $c(32'sh14)
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: $c(32'sh1e)));
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$c(;);
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$display("%d", $c(0));
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$fopen(72'h2f6465762f6e756c6c);
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$fclose(t.fd);
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$fopen(72'h2f6465762f6e756c6c, 8'h72);
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$fgetc(t.fd);
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$fflush(t.fd);
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$fscanf(t.fd, "%d", t.sum);
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;
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$fdisplay(32'h69203d20, "%d", t.sum);
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$fwrite(t.fd, "hello");
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$readmemh(t.fd, t.array);
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$readmemh(t.fd, t.array, 32'sh0);
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$readmemh(t.fd, t.array, 32'sh0, 32'sh0);
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t.sum = 32'sh0;
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t.unnamedblk3.i = 32'sh0;
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begin : label0
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while ((t.unnamedblk3.i < t.cyc)) begin
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t.sum = (t.sum + t.unnamedblk3.i);
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if ((32'sha < t.sum)) begin
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disable label0;
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end
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else begin
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t.sum = (32'sh1 + t.sum);
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end
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t.unnamedblk3.i = (32'h1 + t.unnamedblk3.i);
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end
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end
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if ((32'sh63 == t.cyc)) begin
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$finish;
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end
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if ((32'sh64 == t.cyc)) begin
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$stop;
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end
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if (in) begin
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$display("1");
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end
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else begin
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$display("default");
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end
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if (in) begin
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$display("1");
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end
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else begin
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$display("default");
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end
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if (in) begin
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$display("1");
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end
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else begin
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$display("default");
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end
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if (in) begin
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$display("1");
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end
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else begin
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$display("default");
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end
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if (in) begin
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$display("1");
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end
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else begin
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$display("0");
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end
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priority if (in) begin
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$display("1");
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end
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else begin
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$display("0");
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end
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unique if (in) begin
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$display("1");
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end
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else begin
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$display("0");
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end
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unique0 if (in) begin
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$display("1");
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end
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else begin
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$display("0");
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end
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$display("%d%d", t._Vpast_0_0t._Vpast_1_0,
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t._Vpast_1_0);
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t.str = $sformatf("cyc=%~", t.cyc);
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;
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$display("str = %@", t.str);
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$display("%% [%t] [%^] to=%o td=%d", $time$realtime
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$time$time, $realtime$time$time, $time
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$time, $time);
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$sscanf(40'h666f6f3d35, "foo=%d", t.i);
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;
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$printtimescale;
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if ((32'sh5 != t.i)) begin
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$stop;
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end
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t.sum =
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???? // RAND
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32'sha;
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$display("%g", $log10(t.r));
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$display("%g", $ln(t.r));
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$display("%g", $exp(t.r));
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$display("%g", $sqrt(t.r));
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$display("%g", $floor(t.r));
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$display("%g", $ceil(t.r));
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$display("%g", $sin(t.r));
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$display("%g", $cos(t.r));
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$display("%g", $tan(t.r));
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$display("%g", $asin(t.r));
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$display("%g", $acos(t.r));
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$display("%g", $atan(t.r));
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$display("%g", $sinh(t.r));
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$display("%g", $cosh(t.r));
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$display("%g", $tanh(t.r));
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$display("%g", $asinh(t.r));
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$display("%g", $acosh(t.r));
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$display("%g", $atanh(t.r));
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end
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/*verilator public_flat_rw @(posedge clk)@(negedge
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clk) t.pubflat*/
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t._Vpast_0_0 <= t.cyc;
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end
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t._Vpast_1_0 <= t.cyc;
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end
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__Vdly__t._Vpast_1_0 = t._Vpast_1_0;
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t._Vpast_1_0 = __Vdly__t._Vpast_1_0;
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__Vdly__t._Vpast_0_0 = t._Vpast_0_0;
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t._Vpast_0_0 = __Vdly__t._Vpast_0_0;
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__Vdly__t.r = t.r;
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t.r = __Vdly__t.r;
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__Vdly__t.cyc = t.cyc;
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t.cyc = __Vdly__t.cyc;
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__Vdly__t.pubflat_r = t.pubflat_r;
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t.pubflat_r = __Vdly__t.pubflat_r;
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always @(negedge clk) begin
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$display("negedge clk, pfr = %x", t.pubflat_r);
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end
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signed int [31:0] __Vtask_t.sub.inc__2__i;
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signed int [31:0] __Vtask_t.sub.inc__2__o;
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signed int [31:0] __Vfunc_t.sub.f__3__Vfuncout;
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signed int [31:0] __Vfunc_t.sub.f__3__v;
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logic [15:0] __Vdly__t.pubflat_r;
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signed int [31:0] __Vdly__t.cyc;
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signed real __Vdly__t.r;
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signed int [31:0] __Vdly__t._Vpast_0_0;
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signed int [31:0] __Vdly__t._Vpast_1_0;
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endmodule
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package Vt_debug_emitv___024unit;
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endpackage
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package Vt_debug_emitv_Pkg;
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endpackage
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class Vt_debug_emitv___024unit__03a__03aCls;
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signed int [31:0] member;
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???? // CFUNC '__VnoInFunc_method'
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???? // CFUNC 'new'
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$_CSTMT(_ctor_var_reset(vlSymsp);
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);
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$unit::Cls.member = 32'sh1;
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endclass
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/*class*/package Vt_debug_emitv___024unit__03a__03aCls__Vclpkg;
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end/*class*/package
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