forked from github/verilator
43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic q [$];
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int cycle = 0;
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always @(posedge clk) begin
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cycle <= cycle + 1'b1;
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end
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always @(posedge clk) begin
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q.push_front(1'b1);
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end
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// Important this is a separate always to expose bug where "q" thought unused
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always @(posedge clk) begin
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if (cycle == 1) begin
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if (q.pop_back() != 1) $stop;
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end
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end
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always @(posedge clk) begin
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if (cycle == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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