forked from github/verilator
33 lines
658 B
Systemverilog
33 lines
658 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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class Cls;
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int que[$];
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task push_data(int val);
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que.push_back(val);
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endtask
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endclass
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initial begin
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Cls c2 [1:0];
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c2[0] = new();
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c2[0].push_data(20); // Works
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if (c2[0].que.size() != 1) $stop;
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c2[0].que.push_back(10); // Unsupported
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if (c2[0].que.size() != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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