forked from github/verilator
20 lines
315 B
Systemverilog
20 lines
315 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//See bug289
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`define A1(x)
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`define A2(x,y)
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`A1
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`A1(1,2)
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`A2
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`A2(1)
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`A2(1,2,3)
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module t;
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endmodule
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