forked from github/verilator
66 lines
1.2 KiB
Systemverilog
66 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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endclass
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class BasedA extends Base;
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endclass
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class BasedB extends Base;
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endclass
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module t (/*AUTOARG*/);
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int i;
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int a;
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int ao;
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Base b;
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Base bo;
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BasedA ba;
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BasedA bao;
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BasedB bb;
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BasedB bbo;
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initial begin
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a = 1234;
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i = $cast(ao, a);
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if (i != 1) $stop;
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if (ao != 1234) $stop;
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a = 12345;
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$cast(ao, a);
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if (ao != 12345) $stop;
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i = $cast(ao, 2.1 * 3.7);
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if (i != 1) $stop;
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if (ao != 8) $stop;
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i = $cast(bo, null);
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if (i != 1) $stop;
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if (bo != null) $stop;
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ba = new;
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b = ba;
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i = $cast(bao, b);
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if (i != 1) $stop;
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if (b != ba) $stop;
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bb = new;
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b = bb;
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i = $cast(bbo, b);
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if (i != 1) $stop;
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if (b != bb) $stop;
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bb = new;
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b = bb;
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bao = ba;
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i = $cast(bao, b);
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if (i != 0) $stop;
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if (bao != ba) $stop; // Unchanged
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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